1. Field of the Invention
This invention relates to a CMOS integrated circuit having an EPROM incorporated therein, and to a method of making the same. More particularly, this invention relates to an EPROM structure that is manufacturable using precisely the same process steps that are used to make a small geometry, i.e., high density, CMOS integrated circuit. In other words, no steps need be added to or subtracted from those used in making the small geometry CMOS integrated circuit. Accordingly, the EPROM can be made on the same chip as the small geometry CMOS transistors without compromising the CMOS transistors in any way, especially their speed of operation.
2. Description of the Prior Art
As indicated above, this invention relates to a high density CMOS integrated circuit having an EPROM (electrically programmable read only memory) device. The term "CMOS" is used in its usual context, but is also hereinafter defined for completeness of disclosure. An "EPROM" is a nonvolatile memory integrated circuit unit. It is thus an integrated circuit that has a memory that remains without the need of a power source. Hence, it is a lasting, or permanent, memory. As indicated by its name, an EPROM nonvolatile memory unit can be electrically programmed after manufacture. In addition, the programming, i.e., also the memory, can be erased as a single block by exposing the EPROM chip to ultraviolet light.
The EPROM is not to be confused with an EEPROM (electrically erasable programmable read only memory) device. An EEPROM is thus a nonvolatile memory integrated circuit unit. However, its programming can be selectively changed, i.e., erased, at each of its MOS transistor memory gates. Moreover, the EEPROM programming is changed electrically, not by the application of ultraviolet light. This requires additional process steps on an integrated circuit chip, which increases its cost significantly.
The EPROM and EEPROM nonvolatile memory integrated circuits are comprised of special types of MOS (metal oxide semiconductor) transistors that are often arranged in arrays. As is known, MOS transistors are also referred to as insulated gate field effect transistors (IGFETs). An IGFET has a control gate electrode that is disposed over a channel region that extends between spaced but adjacent source and drain regions embedded in a semiconductor surface. IGFETs of an EPROM and EEPROM memory array are a special form of IGFET in that they also have a second gate electrode. We sometimes herein refer to such IGFETs as EPROM transistors. The second gate electrode of such transistors is an electrically floating electrode that is disposed above the IGFET channel region but below the control gate electrode hereinbefore mentioned. It is electrically floating because it is electrically insulated from the control gate above it and the channel region below it, and has no electrical conductor for accessing it. An electrical charge is normally placed on the floating gate by the effects of tunneling or avalanche injection. Once an electrical charge is placed on the floating gate, the charge is trapped there until it is deliberately removed in some way.
The trapped charge on the floating gate raises the threshold voltage of the underlying channel region of that IGFET. This raises the "turn on" voltage of that IGFET to a value above the voltage usually applied to turn that IGFET "on". Accordingly, that IGFET stays "off" even when a normal turn on voltage is applied to its gate. A floating gate IGFET memory unit of an EPROM or EEPROM memory array is thus "programmed" from a "one" to a "zero" by charging its floating gate. Selected floating gate IGFETs in an EPROM or EEPROM memory array which have been so programmed, will not turn on when the usual "turn on" voltage is applied to them. So programming the selected IGFETs of an EPROM or EEPROM memory array is also referred to herein as programming the EPROM or EEPROM memory. Such "programming" can be erased, i.e., removed, by exposing an EPROM or EEPROM memory array to ultraviolet light, which allows the trapped charge on the floating gate of each programmed IGFET to escape. Such "programming" of an EEPROM can more conveniently be erased electrically by applying an appropriate electrical potential between the control (or "charging") gate and the channel of each programmed IGFET.
The related U.S. Pat. No. 5,014,098 relates to forming an EEPROM in a CMOS integrated circuit. It discusses the difficulties of the past in including nonvolatile memory devices in high density CMOS integrated circuit applications. In order to achieve high packing density, the cell size of the nonvolatile memory was minimized. One convenient way to reduce the cell size was to use a high programming voltage, allowing the capacitance between the control (or "charging") gate and the floating gate to be small. For Fowler-Nordheim tunneling, the tunnel oxide current equation dictates an absolute value of voltage required to pass tunnel current through it for a given tunnel oxide thickness. To obtain this voltage on the floating gate, the control gate voltage has to be increased when the ratio of control gate/floating gate capacitance to floating gate/substrate capacitance is small. Also, for such tunneling to occur, a portion of the oxide between the floating gate and the channel must be thinner than is ordinarily used in the high density CMOS transistors.
The voltage applied to the floating gate (to achieve programming) is determined by the voltage applied to the control gate, and the ratio of (a) the control gate to floating gate capacitance to (b) the floating gate to substrate capacitance. This is what we mean by programming capacitance ratio. As the programming capacitance ratio increases, the programming voltage reduces. In other words, with a higher programming capacitance ratio, a lower control gate voltage can be used to trap enough charge on the floating gate to noticeably raise IGFET threshold voltage.
The capacitive ratio is primarily affected by the layout of the cell, i.e., a larger cell size will typically have a larger capacitance ratio. U.S. Pat. No. 5,014,098, shows that the floating gate and the control gate can be laid out with integral mutually overlapping plate-like enlargements that extend up onto field oxide adjacent the channel region of the EEPROM IGFET from which they extend. This increases the capacitance between the two gates without significantly increasing the floating gate to substrate (i.e., channel) capacitance.
There are many applications where it is desirable to combine nonvolatile memory with CMOS logic circuits. CMOS logic circuits are formed of complementary MOS transistors, or IGFETs. By complementary, we mean that the MOS transistors include both n-channel and p-channel MOS transistors. If one desires to make such logic circuits in high density (for high performance logic), the high density, i.e., small geometry, nonvolatile memory must be designed with relatively deep source and drain junctions and thick field oxides, to accommodate high voltage programming. On the other hand, high density CMOS ideally should have shallow junctions, thinner gate oxides and thinner field oxides, because it would operate at 5 volts or less. Attempts to integrate even small amounts of such high density nonvolatile memory circuity with a high density CMOS logic circuitry, necessitates that the entire integrated circuit be dominated in some key respects by the requirements of the nonvolatile memory high voltage circuitry. The nonvolatile memory requirements tend to degrade the performance and reliability of the high density and low voltage CMOS logic, which typically has shallow source and drain junctions, thinner gate oxides and thinner field oxides. The high voltage junctions used in the nonvolatile memory devices require deeper diffusions, which leads to longer channel lengths for the CMOS logic, to avoid short channel effects. This is undesirable since it results in slower logic devices. The thick field oxide of the nonvolatile memory devices increases the lateral encroachment, or "birds beak", in the CMOS logic. Hence, a greater limitation is present in the minimum pitch of doped regions. Another, and longer range, result of this is the limited shrinkability of such an integrated circuit device and process with a high density/high voltage nonvolatile memory device included.
At present, when forming a CMOS logic circuit with an EPROM or EEPROM device in a stacked polycrystalline silicon FLOTOX technology, i.e., polycrystalline silicon gates and a thin insulator for electron tunneling, compromises are required in order to insure that one of the polycrystalline layers of the nonvolatile memory device can be shared with the logic devices. This is usually done in one of two ways. One method is to first define the floating gate of the EPROM or EEPROM. A high temperature dielectric oxide is then grown which also serves as the gate oxide of the CMOS devices and the control gate dielectric of the nonvolatile memory device. Then the second layer of polycrystalline silicon is used to form the CMOS gates and the nonvolatile memory control gate. Thus, the same layer of polycrystalline silicon is shared for the control gate of the nonvolatile memory device and the CMOS gates. In this method, formation of the high temperature dielectric oxide for the CMOS and control gate tends to degrade the characteristics of the tunnel oxide in the nonvolatile memory device. This high temperature also shifts the implants in the CMOS devices, and thus creates a shift in the electrical characteristics of the resultant CMOS devices from what the original MOS process would produce without inclusion of the nonvolatile memory device processing. Also, it is difficult to make a reliable gate dielectric from the silicon dioxide grown between the floating gate and the control gate of the nonvolatile memory device.
The second method is to grow the gate oxide and then mask and etch the windows for the tunnel oxide. A pre-cleaning step for growth of the tunnel oxide then follows. The tunnel oxide is then grown, followed by a pre-polycrystalline silicon deposition cleaning step and a polycrystalline silicon deposition step. The first polycrystalline silicon layer is shared between the CMOS devices and the floating gate of the nonvolatile memory device. In this latter prior art method, the steps required between the gate oxidation and polycrystalline silicon deposition degrade the gate oxide and thus the performance of the CMOS circuit. The gate oxide is degraded by placing photoresist on it for the tunnel mask, the pre-tunnel oxide clean, and the tunnel oxidation itself. These steps may introduce contaminants into the gate oxide, and will certainly alter the thickness of the gate oxide during the tunnel oxidation.
It is therefore desirable to have a high reliability CMOS logic circuit in which a nonvolatile memory device can be included with negligible impact on both the CMOS circuit and the nonvolatile memory device. The related U.S. Pat. No. 5,014,098 shows how an EEPROM can be so included by adding process steps to the usual CMOS process that only have negligible impact on the CMOS devices. On the other hand, it is to be noted that additional process steps do in fact have to be included, which increases cost of the process, and might slightly reduce yields. In addition, the added conductor pattern needed for electrically erasing an EEPROM, significantly expands the size an EEPROM nonvolatile memory unit over that of an EPROM nonvolatile memory. This can increase cost significantly.
As indicated above, the nonvolatile memory device that is made in the related U.S. Pat. No. 5,014,098 is an EEPROM, not an EPROM. An electrical charge can be put on its floating gate by any one of several techniques, including the Fowler-Nordheim Tunneling action shown in the related U.S. Pat. No. 5,014,098. However, Fowler-Nordheim Tunneling requires that a spot of the gate oxide on the channel region be thinner than normal gate oxide. As also indicated above, this requires adding special steps to the process used to make the CMOS integrated circuit, to form the thinner oxide. However, the addition of the extra steps is offset by the benefit that the thinner oxide also permits electrical erasing by Fowler-Nordheim Tunneling, as disclosed in the related U.S. Pat. No. 5,014,098. Hence, Fowler-Nordheim Tunneling permits easy, fully electrical, reprogramming of the EEPROM on a selective IGFET basis.
We have now recognized that electrical erasing of a PROM is often not needed. In fact, no erasing at all may be needed, or that erasing prior to encapsulation is all that might be needed. In addition, we have recognized that block erasing, as opposed to selective IGFET erasing, may be satisfactory in many applications. Accordingly, we have recognized that an EPROM nonvolatile memory may be as useful as an EEPROM nonvolatile memory in many applications. Further, we have recognized that avalanche injection can be used to charge the floating gate of an EPROM using normal "gate" oxide thicknesses, i.e., oxide thickness between the floating gate and its underlying channel region. Still further, we have recognized that avalanche injection into the floating gate of an EPROM can he done at low voltages if the control gate/floating gate to floating gate/substrate capacitance ratio is about two or greater. Still further, we have found that an EPROM can be included in a high performance CMOS integrated circuit unit using exactly the same process steps as are used to make the high performance CMOS transistors in such a unit. In other words, no steps need to be added to or subtracted from the high performance CMOS process in order to also make the EPROM on the same chip. All that is needed is to include our special EPROM structure features in selected ones of the masks used to make the CMOS circuitry. Accordingly, in our invention, a nonvolatile memory unit can be included in a CMOS integrated circuit made with two micron or less design rules, without any penalties or compromises at all in the CMOS circuitry.